TY  CONF
TI  THE SYNTHESIS OF MEMORY ELEMENTS FOR CMOS CIRCUITS
KW  D–flip-flop
KW  E-flip-flop
KW  JK-flip-flop
KW  standard logic element
KW  power dissipation
KW  performance of the circuit
KW  energy–topological criterion
KW  the circuit simulation
JO  CAD/EDA/SIMULATION IN MODERN ELECTRONICS 2019
AU  Kulakova, A.A.
AU  Lukyanenko, E.B.
PY  2024
PB  Bryansk State Technical University